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A linear model for high-level delay estimation in VDSM on-chip interconnects

Murgan, Tudor and Garcia Ortiz, Alberto and Petrov, Mihail and Glesner, Manfred (2005):
A linear model for high-level delay estimation in VDSM on-chip interconnects.
Piscataway, NJ, IEEE Service Center, In: Conference proceedings / IEEE International Symposium on Circuits and Systems (ISCAS) : May 23 - 26, 2005, International Conference Center, Kobe, Japan / cosponsored by the Institute of Electrical and Electronics Engineers, Circuits and Systems Society .., [Conference or Workshop Item]

Item Type: Conference or Workshop Item
Erschienen: 2005
Creators: Murgan, Tudor and Garcia Ortiz, Alberto and Petrov, Mihail and Glesner, Manfred
Title: A linear model for high-level delay estimation in VDSM on-chip interconnects
Language: English
Series Name: Conference proceedings / IEEE International Symposium on Circuits and Systems (ISCAS) : May 23 - 26, 2005, International Conference Center, Kobe, Japan / cosponsored by the Institute of Electrical and Electronics Engineers, Circuits and Systems Society ..
Place of Publication: Piscataway, NJ
Publisher: IEEE Service Center
Divisions: 18 Department of Electrical Engineering and Information Technology
Date Deposited: 20 Nov 2008 08:24
License: [undefiniert]
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