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A makefile generator for VHDL models under consideration of hierarchical names, identifier-visibility and identifier-hiding

Ecker, Wolfgang and Mades, J. and Schneider, T. and Windisch, A. and Yang, K. (1999):
A makefile generator for VHDL models under consideration of hierarchical names, identifier-visibility and identifier-hiding.
In: Forum of Design Languages <1999, Lyon>: Proceedings, [Conference or Workshop Item]

Item Type: Conference or Workshop Item
Erschienen: 1999
Creators: Ecker, Wolfgang and Mades, J. and Schneider, T. and Windisch, A. and Yang, K.
Title: A makefile generator for VHDL models under consideration of hierarchical names, identifier-visibility and identifier-hiding
Language: English
Series Name: Forum of Design Languages <1999, Lyon>: Proceedings
Divisions: 18 Department of Electrical Engineering and Information Technology
Date Deposited: 19 Nov 2008 16:22
License: [undefiniert]
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