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Sequential equivalence checking by symbolic simulation

Ritter, Gerd (2000):
Sequential equivalence checking by symbolic simulation.
In: Formal methods in computer aided design: 3rd International Conference, 2000, Austin, Texas; Proceedings. Hrsg.: R. Hunt (et al.). - Berlin, Heidelberg (u.a.): Springer, 2000 = Lecture notes in computer science; 1954, Berlin, Heidelberg (u.a.), Springer, [Conference or Workshop Item]

Item Type: Conference or Workshop Item
Erschienen: 2000
Creators: Ritter, Gerd
Title: Sequential equivalence checking by symbolic simulation
Language: German
Series Name: Formal methods in computer aided design: 3rd International Conference, 2000, Austin, Texas; Proceedings. Hrsg.: R. Hunt (et al.). - Berlin, Heidelberg (u.a.): Springer, 2000 = Lecture notes in computer science; 1954
Place of Publication: Berlin, Heidelberg (u.a.)
Publisher: Springer
Divisions: 18 Department of Electrical Engineering and Information Technology
Date Deposited: 19 Nov 2008 16:22
License: [undefiniert]
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