Schwarz, Alexander ; Hochberger, Christian
Hochberger, Christian ; Bauer, Lars ; Pionteck, Thilo (eds.) (2021):
Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode.
In: Lecture Notes in Computer Science, 12800, In: Architecture of Computing Systems, pp. 103-117,
Springer, 34th International Conference on Architecture of Computing Systems, virtual Conference, 07.-08.07.2021, ISBN 978-3-030-81682-7,
DOI: 10.1007/978-3-030-81682-7_7,
[Conference or Workshop Item]
Abstract
Java Bytecode is used as binary format for a number of programming languages and programming systems. Since Java virtual machines exist for many platforms, it can be regarded as a universal execution format. Consequently, several hardware implementations of Bytecode processors exist. Unfortunately, they all suffer from the inefficiencies of the Bytecode principle. Particularly, the operand stack and the local variable storage are bottlenecks during execution. In this contribution, we evaluate the performance gain that can be achieved by replacing Bytecode with a data flow oriented instruction set architecture (ISA). We describe the changes that are necessary to adapt an existing Bytecode processor to the new ISA. Ultimately, we compare execution times and HW resources for both processors, which are based on identical ALUs and heap memory model. Execution times are evaluated using the SPEC JVM98 benchmark and a set of micro benchmarks which have a very flat call graph. SPEC JVM98 reaches a speedup of 1.76 and the micro benchmarks even gain a factor of 2.80.
| Item Type: | Conference or Workshop Item |
|---|---|
| Erschienen: | 2021 |
| Editors: | Hochberger, Christian ; Bauer, Lars ; Pionteck, Thilo |
| Creators: | Schwarz, Alexander ; Hochberger, Christian |
| Title: | Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode |
| Language: | English |
| Abstract: | Java Bytecode is used as binary format for a number of programming languages and programming systems. Since Java virtual machines exist for many platforms, it can be regarded as a universal execution format. Consequently, several hardware implementations of Bytecode processors exist. Unfortunately, they all suffer from the inefficiencies of the Bytecode principle. Particularly, the operand stack and the local variable storage are bottlenecks during execution. In this contribution, we evaluate the performance gain that can be achieved by replacing Bytecode with a data flow oriented instruction set architecture (ISA). We describe the changes that are necessary to adapt an existing Bytecode processor to the new ISA. Ultimately, we compare execution times and HW resources for both processors, which are based on identical ALUs and heap memory model. Execution times are evaluated using the SPEC JVM98 benchmark and a set of micro benchmarks which have a very flat call graph. SPEC JVM98 reaches a speedup of 1.76 and the micro benchmarks even gain a factor of 2.80. |
| Title of Book: | Architecture of Computing Systems |
| Series Name: | Lecture Notes in Computer Science |
| Volume: | 12800 |
| Publisher: | Springer |
| ISBN: | 978-3-030-81682-7 |
| Divisions: | 18 Department of Electrical Engineering and Information Technology 18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering 18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering > Computer Systems Group |
| Event Title: | 34th International Conference on Architecture of Computing Systems |
| Event Location: | virtual Conference |
| Event Dates: | 07.-08.07.2021 |
| Date Deposited: | 09 Aug 2021 07:16 |
| DOI: | 10.1007/978-3-030-81682-7_7 |
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