Ernst, Markus ; Klupsch, Steffen ; Hauck, Oliver ; Huss, Sorin (2001)
Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems.
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
A generator-based design and validation methodology for rapid prototyping of elliptic curve public-key cryptosystem hardware is described. By their very nature, crypto systems challenge both design and validation. Pure RTL-based synthesis is as unsuitable as is high-level synthesis. Instead, a generator program accepts the two main parameters, key size and multiplier radix, and creates a highly efficient custom RTL description which is synthesized into a FPGA. This approach benefits the design in that it allows to effortlessly exploit the available resources on the FPGA for variable requirements of security and performance. It is also advantageous for validation of the correctness of the design as for small parameter values the design can be tested exhaustively. Thus, the correctness for large key sizes depends only on the correctness of the generator. Furthermore, deploying FPGAs supports integration of an ASIC realisation of the same algorithm which boosts performance...
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2001 |
| Autor(en): | Ernst, Markus ; Klupsch, Steffen ; Hauck, Oliver ; Huss, Sorin |
| Art des Eintrags: | Bibliographie |
| Titel: | Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems |
| Sprache: | Englisch |
| Publikationsjahr: | Juni 2001 |
| Buchtitel: | Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping |
| Kurzbeschreibung (Abstract): | A generator-based design and validation methodology for rapid prototyping of elliptic curve public-key cryptosystem hardware is described. By their very nature, crypto systems challenge both design and validation. Pure RTL-based synthesis is as unsuitable as is high-level synthesis. Instead, a generator program accepts the two main parameters, key size and multiplier radix, and creates a highly efficient custom RTL description which is synthesized into a FPGA. This approach benefits the design in that it allows to effortlessly exploit the available resources on the FPGA for variable requirements of security and performance. It is also advantageous for validation of the correctness of the design as for small parameter values the design can be tested exhaustively. Thus, the correctness for large key sizes depends only on the correctness of the generator. Furthermore, deploying FPGAs supports integration of an ASIC realisation of the same algorithm which boosts performance... |
| Fachbereich(e)/-gebiet(e): | 20 Fachbereich Informatik 20 Fachbereich Informatik > Integrierte Schaltungen und Systeme |
| Hinterlegungsdatum: | 31 Dez 2016 00:15 |
| Letzte Änderung: | 03 Jun 2018 21:31 |
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