Malipatlolla, Sunil ; Huss, Sorin (2010)
A Novel Technique for FPGA IP Protection.
Konferenzveröffentlichung, Bibliographie
Kurzbeschreibung (Abstract)
The configuration data sequence of a field programmable gate array (FPGA) is an intellectual property (IP) of the original designer. With the increase in deployment of FPGAs in modern embedded systems, the IP protection of FPGA hardware designs has become a necessary requirement for many IP vendors. There have been already many proposals to overcome this problem using symmetric encryption techniques but these methods need a cryptographic key to be stored in a non-volatile memory located on FPGA or in a battery-backed RAM (Random Access Memory) as done in some of the current FPGAs. The expenses with the proposed methods are, occupation of larger area on FPGA in the former case and limited lifetime of the device in the latter. In contrast, we propose a novel method which combines the dynamic partial reconfiguration (dynamic PR) feature of an SRAM-based FPGA with the public key cryptography (PKC) to protect the FPGA configuration files without the need to store any keys on FPGA.
| Typ des Eintrags: | Konferenzveröffentlichung |
|---|---|
| Erschienen: | 2010 |
| Autor(en): | Malipatlolla, Sunil ; Huss, Sorin |
| Art des Eintrags: | Bibliographie |
| Titel: | A Novel Technique for FPGA IP Protection |
| Sprache: | Englisch |
| Publikationsjahr: | September 2010 |
| Buchtitel: | Systems and Network Security Doctoral Workshop, 55th International Scientific Colloquium (IWK 2010), TU Ilmenau |
| Kurzbeschreibung (Abstract): | The configuration data sequence of a field programmable gate array (FPGA) is an intellectual property (IP) of the original designer. With the increase in deployment of FPGAs in modern embedded systems, the IP protection of FPGA hardware designs has become a necessary requirement for many IP vendors. There have been already many proposals to overcome this problem using symmetric encryption techniques but these methods need a cryptographic key to be stored in a non-volatile memory located on FPGA or in a battery-backed RAM (Random Access Memory) as done in some of the current FPGAs. The expenses with the proposed methods are, occupation of larger area on FPGA in the former case and limited lifetime of the device in the latter. In contrast, we propose a novel method which combines the dynamic partial reconfiguration (dynamic PR) feature of an SRAM-based FPGA with the public key cryptography (PKC) to protect the FPGA configuration files without the need to store any keys on FPGA. |
| Freie Schlagworte: | Secure Things;FPGA, Bitstream, Public Key Cryptography, Dynamic Partial Reconfiguration, IP, Embedded Systems |
| Fachbereich(e)/-gebiet(e): | LOEWE > LOEWE-Zentren > CASED – Center for Advanced Security Research Darmstadt LOEWE > LOEWE-Zentren LOEWE |
| Hinterlegungsdatum: | 31 Dez 2016 00:15 |
| Letzte Änderung: | 17 Mai 2018 13:02 |
| PPN: | |
| Export: | |
| Suche nach Titel in: | TUfind oder in Google |
 |
Frage zum Eintrag |
Optionen (nur für Redakteure)
 |
Redaktionelle Details anzeigen |
Drucken
Impressum