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GarbledCPU: A MIPS Processor for Secure Computation in Hardware

Songhori, Ebrahim ; Zeitouni, Shaza ; Dessouky, Ghada ; Schneider, Thomas ; Sadeghi, Ahmad-Reza ; Koushanfar, Farinaz :
GarbledCPU: A MIPS Processor for Secure Computation in Hardware.
53rd Design Automation Conference (DAC'16)
[Konferenz- oder Workshop-Beitrag], (2016)

Kurzbeschreibung (Abstract)

We present GarbledCPU, the first framework that realizes a hardware-based general purpose sequential processor for secure computation. Our MIPS-based implementation enables development of applications (functions) in a high-level language while performing secure function evaluation (SFE) using Yao's garbled circuit protocol in hardware. Garbled-CPU provides three degrees of freedom for SFE which allow leveraging the trade-of between privacy and performance: public functions, private functions, and semi-private functions. We synthesize GarbledCPU on a Virtex-7 FPGA as a proof-of-concept implementation and evaluate it on various benchmarks including Hamming distance, private set intersection and AES. Our results indicate that our pipelined hardware framework outperforms the fastest available software implementation.

Typ des Eintrags: Konferenz- oder Workshop-Beitrag (Keine Angabe)
Erschienen: 2016
Autor(en): Songhori, Ebrahim ; Zeitouni, Shaza ; Dessouky, Ghada ; Schneider, Thomas ; Sadeghi, Ahmad-Reza ; Koushanfar, Farinaz
Titel: GarbledCPU: A MIPS Processor for Secure Computation in Hardware
Sprache: Deutsch
Kurzbeschreibung (Abstract):

We present GarbledCPU, the first framework that realizes a hardware-based general purpose sequential processor for secure computation. Our MIPS-based implementation enables development of applications (functions) in a high-level language while performing secure function evaluation (SFE) using Yao's garbled circuit protocol in hardware. Garbled-CPU provides three degrees of freedom for SFE which allow leveraging the trade-of between privacy and performance: public functions, private functions, and semi-private functions. We synthesize GarbledCPU on a Virtex-7 FPGA as a proof-of-concept implementation and evaluate it on various benchmarks including Hamming distance, private set intersection and AES. Our results indicate that our pipelined hardware framework outperforms the fastest available software implementation.

Buchtitel: 53rd Design Automation Conference (DAC'16)
Freie Schlagworte: ICRI-SC;S2;E4;Secure Protocols;Primitives;P3
Fachbereich(e)/-gebiet(e): 20 Fachbereich Informatik
20 Fachbereich Informatik > Engineering Cryptographic Protocols (ENCRYPTO)
20 Fachbereich Informatik > Kryptographische Protokolle
20 Fachbereich Informatik > Systemsicherheit
DFG-Sonderforschungsbereiche (inkl. Transregio)
DFG-Sonderforschungsbereiche (inkl. Transregio) > Sonderforschungsbereiche
Profilbereiche
Profilbereiche > Cybersicherheit (CYSEC)
LOEWE
LOEWE > LOEWE-Zentren
LOEWE > LOEWE-Zentren > CASED – Center for Advanced Security Research Darmstadt
20 Fachbereich Informatik > EC SPRIDE
20 Fachbereich Informatik > EC SPRIDE > Engineering Cryptographic Protocols (am 01.03.18 aufgegangen in ENCRYPTO)
DFG-Sonderforschungsbereiche (inkl. Transregio) > Sonderforschungsbereiche > SFB 1119: CROSSING – Kryptographiebasierte Sicherheitslösungen als Grundlage für Vertrauen in heutigen und zukünftigen IT-Systemen
Hinterlegungsdatum: 04 Aug 2016 10:13
ID-Nummer: TUD-CS-2016-0042
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